1. Background of the Invention
The present invention generally relates to semiconductor integrated circuit devices and methods for testing the devices. More particularly, the present invention is concerned with a semiconductor integrated circuit device having a flat-type on-chip step-down power supply circuit, and a method for performing a burn-in (acceleration) test in which an external power supply voltage exceeding the normal operation range is applied to the device in order to detect initial faults in the device.
A recent requirement of increasing the integration density of semiconductor integrated circuit devices need more miniaturized MOS transistors formed in the device. The miniaturized MOS transistors may encounter a problem about reliability. More particularly, the miniaturized MOS transistors have an increased electric field between the source and drain, which causes a hot carrier functioning to prevent the transistors from performing the transistor operation.
Recently, there has been proposed a semiconductor integrated circuit device equipped with an on-chip step-down power supply circuit in order to ensure resistivity to the hot carrier. The on-chip step-down power supply circuit receives an external power supply voltage and steps it down to thereby generate a reduced power supply voltage.
Though various on-chip step-down power supply circuits are known, they can be grouped into the following two types:
(1) a flat-type circuit capable of maintaining the step-down voltage at an approximately constant level even if the external power supply voltage varies; and PA1 (2) a circuit generating the step-down voltage varying based on a variation in the external power supply voltage. PA1 a flat-range voltage supply unit which steps down an external power supply voltage and generates a resultant, flat-range voltage; PA1 a burn-in voltage supply unit which generates a burn-in voltage depending on the external power supply voltage; PA1 a switching unit which selects either the flat-range voltage or the burn-in voltages a selected voltage being supplied to an internal circuit; and PA1 a switching instruction unit which includes switches and generates a switching instruction signal by an ON/OFF control of the switches; and PA1 a switching control unit which controls the switching unit in accordance with the switching instruction signal. PA1 flat-range voltage supply unit which steps down an external power supply voltage and generates a resultant, flat-range voltage; PA1 a burn-in voltage supply unit which generates a burn-in voltage depending on the external power supply voltage; PA1 a switching unit which selects either the flat-range voltage or the burn-in voltage, a selected voltage being supplied to an internal circuit; and PA1 a switching instruction unit which includes first and second switches and generates a switching instruction signal by an ON/OFF control of the first and second switches; and PA1 a switching control unit which controls the switching unit in accordance with the switching instruction signal, the method comprising the steps of:
As compared with the latter type, the step-down power supply circuit of the flat type is widely employed because the step-down voltage internally generated is maintained at an approximately constant level irrespective of a variation in the external power supply voltage and contributes to stability of the performance.
However, a problem will occur when a burn-in test (voltage accelerating test) is carried out for semiconductor devices equipped with the flat-type step-down circuit. In the burn-in test, a voltage exceeding the normal operation voltage range for internal circuits on the chip is applied to the device for a predetermined time. The normal transistors forming the internal circuits are not affected by such a high voltage. Defective transistors are rapidly degraded. After the application of the high voltage, it is determined whether there are such defective transistors. The devices having defective transistors are discarded. When the high-voltage for the burn-in test is applied to the semiconductor device equipped with the flat-type step-down power supply circuit, the circuit does not produce the step-down voltage higher than the normal operation voltage. Hence, the burn-in test cannot be carried out for semiconductor devices equipped with the flat-type step-down power supply circuits. Hence, it is desired that the above problem be overcome.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an on-chip step-down power supply circuit related to the present invention. A regulator unit 14 receives an input voltage V.sub.D and supplies a regulated power supply voltage to an internal circuit (not shown for the sake of simplicity). A flat-range voltage supply unit 11 includes a resistor R0, N-channel MOS transistors Q1 through Q4 connected in the diode formation, P-channel MOS transistors Q5 and Q6 used to form a current-mirror circuit, N-channel MOS transistors Q7 through Q9, and a P-channel MOS transistor Q10.
The resistor R0 and the transistors Q1 through Q4 form a series circuit provided between a Vcc (an external power supply voltage) line 22 and ground. A connection node at which the resistor R0 and the drain and gate of the transistor Q1 are connected together is connected to a terminal 23, and the gates of the transistors Q7 and Q9.
The drains of the transistors Q5 and Q6 are respectively connected to the trains of the transistors Q7 and Q8. The sources of the transistors Q7 and Q8 are commonly connected to the drain of the transistor Q9. The gate of the transistor Q10 is commonly connected to the drains of the transistors Q5 and Q7. The drain of the transistor Q10 is connected to the gate of the transistor Q8.
A burn-in voltage supply unit 12 is made up of a P-channel MOS transistor Q11 for use in switching, P-channel MOS transistors Q12, Q13 and Q14, resistors R1 and R2, and N-channel MOS transistors Q15, Q16 and Q17. The sources of the transistors Q12, Q13 and Q14 are connected to the Vcc line 22. The gate of the transistor Q15 is connected to the drain of the transistor Q12 and the source of the transistor Q11. The drain of the transistor Q15 is connected to the drain and gate of the transistor Q13. The drain of the transistor Q16 is connected to the gate of the transistor Q12 and the drain of the transistor Q14. The gate of the transistor Q16 is connected to the connection node where the resistors R1 and R2 are connected together. The drain of the transistor Q17 is connected to the sources of the transistors Q15 and Q16.
The transistors Q13 and Q14 form a current-mirror circuit. The transistor Q17 forms a constant-current source in which an output reference voltage V.sub.REF obtained at the terminal 23 is applied to the gate thereof via a terminal 24. The resistors R1 and R2 form a voltage divider.
A flat-range voltage releasing signal generating unit 13 is made up of resistors R3 and R4, P-channel MOS transistors Q18, Q19 and Q23, and N-channel MOS transistors Q20, Q21, Q22 and Q24. The resistors R3 and R4 form a voltage divider which divides the external power supply voltage Vcc. The sources of the transistors Q18, Q19 and Q23 are connected to the Vcc line 22. The sources of the transistors Q20 and Q21 are connected together. The drain of the transistor Q22 is connected to the sources of the transistors Q20 and Q21. The gate of the transistor Q24 is connected to the gates of the transistors Q20 and Q22 and a terminal 25. The transistors Q18 and Q19 connected to the drains of the transistors Q20 and Q21 form a current-mirror circuit. The gate of the transistor Q21 is connected to the node at which the resistors R3 and R4 are connected together. The gate of the transistor Q23 is connected to the drains of the transistors Q18 and Q20. Further, the drains of the transistors Q23 and Q24 are connected to the gate of the transistor Q11.
A description will now be given of the operation of the circuit with reference to FIGS. 2A through 2D, which are graphs showing the relation between the internal voltage and the external power supply voltage Vcc.
When the external power supply voltage Vcc is lower than the threshold voltages of the transistors Q1 through Q4, the transistors Q1-Q4 are OFF, and the reference voltage V.sub.REF, equal to the external power supply voltage Vcc, is output via the terminal 23. At this time, the gate potential of the transistor Q8 is balanced with the gate potential of the transistor Q7 and is equal to the external power supply voltage Vcc.
When the external power supply voltage Vcc becomes higher than a voltage Vcc1 corresponding to the threshold voltages of the transistors Q1-Q4, the transistors Q1-Q4 are turned ON, and the reference voltage V.sub.REF regulated at a constant level is output via the terminal 23. The constant reference voltage V.sub.REF is applied to the gate of the transistor Q9, which provides a constant current, and is also applied to the gate of the transistor Q7.
The current mirror circuit formed by the transistors Q5 and Q6 is formed on the drain side of the transistor Q7. Hence, the drain current equal to the drain current of the transistor Q7 flows in the transistor Q8. As a result, the gate potential of the transistor Q8 is balanced at the same potential as the gate potential V.sub.REF of the transistor Q7. Thus, as indicated by the solid line in FIG. 2A, the gate voltage V.sub.A of the transistor Q8 is constant (flat-range voltage) when the external power supply voltage Vcc is equal to or higher than a voltage Vcc1.
The voltage produced by dividing the external power supply voltage Vcc by means of the resistors R1 and R2 is applied to the gate of the transistor Q16. The above-mentioned reference voltage V.sub.REF is applied, via the terminal 24, to the gate of the transistor Q17 provided on the source side of the transistor Q16. Hence, the transistor Q17 functions as a constant-current source.
When the gate potential of the transistor Q16 is increased, the drain current thereof is increased, and the drain current of the transistor Q12 is decreased. Further, the gate potential of the transistor Q15 is increased. When the gate potential of the transistor Q15 becomes equal to the gate potential of the transistor Q16, the transistor Q12 is turned OFF. The identical currents flow in the transistors Q15 and Q16 from the current-mirror circuit of the transistors Q13 and Q14 connected to the drains of the transistors Q15 and Q16. Hence, the circuit becomes the balanced state.
Hence, as indicated by the solid line shown in FIG. 2, the gate voltage V.sub.B becomes equal to the voltage produced by dividing the voltage Vcc applied to the gate of the transistor Q16 by means of the resistors R1 and R2. Hence, the gate voltage V.sub.B is less than the external power supply voltage Vcc, and is varies in proportion to a variation in the voltage Vcc. The voltage V.sub.B is applied, as a burn-in voltage, to the source of the transistor Q11.
The output reference voltage V.sub.REF obtained at the terminal 23 is applied, via the terminal 25, to the gates of the transistors Q20 and Q22 in the flat-range voltage releasing signal generating circuit 13. Hence, the transistor Q22 functions as a current source. The external power supply voltage Vcc is divided by the resistors R3 and R4, and the divided voltage is applied to the gate of the transistor Q21. The voltage dividing ratio defined by the resistors R3 and R4 is set to a predetermined value greater than that defined by the resistors R1 and R2. Hence, the gate voltage of the transistor Q21 changes in accordance with a characteristic line less inclined than that shown in FIG. 2B.
The current-mirror circuit of the transistors Q18 and Q19 connected to the drains of the transistors Q20 and Q21 functions to make the drain currents of the transistors Q20 and Q21 equal to each other. When the gate voltage of the transistor Q21 is lower than the reference voltage V.sub.REF applied to the gate of the transistor Q20, the current flowing in the transistor Q18 becomes equal to the current flowing in the transistor Q19.
At this time, not only the current from the transistor Q18 but also the current from the transistor Q23 flow in the transistor Q20. Thus, the transistor Q23 is ON. Hence, the voltage Vc of the node at which the drains of the transistors Q23 and Q24 are connected together becomes approximately equal to the external power supply voltage Vcc applied to the source of the transistor Q23.
When the external power supply voltage Vcc is equal to a Vcc2, and the gate voltage of the transistor Q21 obtained by dividing the voltage Vcc2 becomes equal to the gate voltage V.sub.REF of the transistor Q20, the currents each equal to half the drain current of the transistor Q22 flows in the transistors Q20 and Q21. Hence, the transistor Q23 is turned OFF. Hence, the above voltage Vc becomes equal to Vss (for example, the ground level), which is the source potential of the transistor Q24 which is ON.
When the external power supply voltage Vcc is equal to or higher than the voltage Vcc2, the transistor Q23 is turned OFF in the above manner, and the voltage Vc becomes low (Vss). Hence, the voltage Vc is varied as indicated by the solid line in FIG. 2C. The voltages Vcc1 and Vcc2 are respectively set to the lower and upper limits of the external power supply voltage Vcc in the normal operation of the semiconductor device.
The voltage Vc is applied to the gate of the transistor Q11, and controls the switching thereof. More particularly, when the external power supply voltage Vcc is equal to or higher than the voltage Vcc2, a flat-range voltage releasing signal at a low level is applied to the gate of the transistor Q11 whereby it is turned ON. When the voltage Vcc is lower than the voltage Vcc2, the flat-range voltage releasing signal at a high level is applied to the gate of the transistor Q11 whereby it is turned OFF.
Hence, when the external power supply voltage Vcc is lower than Vcc2, the transistor Q11 is OFF, and the flat-range voltage V.sub.A from the flat-range voltage supply unit 11 is output to the regulator unit 14. When the external power supply voltage Vcc is equal to or greater than Vcc2, the transistor Q11 is ON, and the voltage V.sub.A is less than the voltage V.sub.B. As a result, the burn-in voltage V.sub.B from the burn-in voltage supply unit 12 is applied to the regulator unit 14 via the transistor Q11.
As a result, the input internal voltage V.sub.D applied to the regulator unit 14 is changed as a function of the external power supply voltage Vcc, as indicated by the solid line shown in FIG. 2D. It can be seen from FIG. 2D that there is the burn-in voltage on a straight line V passing through any value within the normal operation voltage range between Vcc1 and Vcc2 as well as the origin. Hence, in the burn-in test, it is possible to provide the regulator unit 14 with the burn-in voltage in the same ratio with respect to the external power supply voltage Vc as that in the normal operation. In FIG. 2D, the one-dot chained line VI indicates the characteristic of the voltage applied to the gate of the transistor Q21 from the node at which the resistors R3 and R4 are connected together.
As described above, switching between the burn-in voltage and the flat-range voltage is carried out on the basis of the level of the external power supply voltage Vcc. However, the releasing voltage Vcc2 at which the switching takes place fluctuates due to desperation in the production process or the ambient temperature. Hence there is a possibility that an erroneous voltage is applied to the internal circuits. For examples the burn-in voltage is output in the normal operation or the burn-in test cannot be performed.